1. Field of the Invention
The present invention generally relates to programmable logic arrays, and more particularly to high speed programmable logic arrays having reduced delay or skew effects.
2. Description of the Related Art
Logic circuits, particularly those used to simultaneously evaluate an equation with a large number of inputs have been implemented in a variety of architectures. A programmable logic array (PLA) is an integrated circuit device that incorporates fixed sets of AND and OR logic gates or similar functions such as NAND, NOR, XOR or XNOR with one or more interconnect planes used to create several logical combinatorial outputs from several logical inputs. The interconnect planes in a mask programmable logic array are usually metallization layers that can be redesigned and deposited during a production run without redesigning the semiconductor layers of the device. The depositing of the mask can be performed by vapor deposition of aluminum or other metals using techniques well known in the art. The mask connects devices within an interconnect array or "plane" comprising two sets of conductors, a set of logic inputs and a set of logic gate inputs. The sets of conductors are coupled together with devices that create a logic contribution from the logic inputs to the logic gate inputs. Fuse programmable logic arrays allow programming of the device after manufacture by using a programming or appropriate in-circuit electronics to allow programming of the device.
In high speed logic, particularly asynchronous logic where combinatorial outputs are not clocked, it is desirable to eliminate device skew. Device skew is the differential delay between the logical inputs from which the combinatorial outputs are produced. In asynchronous logic, an output is valid only after all of the inputs that form part of the logic equation have propagated through the gates to the output. In synchronous logic, the maximum clocking rate of the device is set by the validity of the combinatorial input to the latch, which is determined by the time it takes for all of the inputs to propagate to the input of the register latching the output. Device skew is undesirable in that a period of uncertainty exists from the time that the fastest logic input asserts an effect on the output to the time that the slowest logic input asserts its affect on the output. If device skew is too great, the use of PLA's may not be practical in certain high-speed circuits, or may lead to improper operation of the PLA.
Circuits using asynchronous or synchronous logic with low device skew can be optimized to consider device delay as part of the overall logic path, since the period of uncertainty is low. On the other hand, circuits with high device skew are less useful in that the period of uncertainty produces an invalid result for that period, making the output unusable as a prior state or a new state for that period of time.
The advantages of using programmable logic arrays include mask reprogrammability, which allows redesign of just the metal mask, and reusability, in that the same programmable logic semiconductor layer design can be used repeatedly to support an unlimited number of designs.
But, programmable logic arrays, especially those implemented in dynamic logic, have device skews that are typically variable and can be quite high. The device skew depends on the particular logic equations being implemented for a given combinatorial logic output and vary from output to output causing output skew which is another similar problem burdening the use of PLA's, as the outputs of the device will not be valid at the same time, further increasing the difficulties of incorporating PLA's in asynchronous circuit design.
It would therefore be desirable to improve mask programmable logic arrays and other topologies so that device skew and output skew can be reduced or eliminated. It would be further desirable to improve the topologies in such a way that the mask layer can be changed without increasing device skew.